1. Field of the Invention
The present invention relates to a method for manufacturing a silicon single crystal wafer that is suitable for fabrication of an image pickup device or a memory device and to an electronic device using this method.
2. Description of the Related Art
A silicon single crystal wafer for use in a semiconductor device is generally sliced out from a silicon single crystal ingot grown by a Czochralski method (which will be referred to as a [CZ method] hereinafter) and manufactured through processes such as polishing. Request items required for this silicon single crystal wafer are formation of a defect-free layer (a Denuded Zone layer: which will be referred to as a [DZ layer] hereinafter) in a surface layer, control over solid solubility oxygen concentration that affects mechanical strength, and control over an oxide precipitate (a Bulk Micro Defect: which will be referred to as a [BMD] hereinafter) formed in the wafer to remove a metal contamination element taken in during a device process from a wafer surface layer portion.
In a general silicon single crystal wafer is present a grown-in defect such as a COP (a Crystal Originated Particle) or an OSF (Oxidation Induced Stacking Fault) nucleus (a micro defect that can be a cause of occurrence of the OSF) produced in a crystal at the stage of growing a silicon single crystal by the CZ method. Therefore, as a method for annihilating the grown-in defect in a wafer surface layer and forming a high-quality DZ layer, a nitrogen (N) added wafer subjected to a high-temperature annealing treatment in an Ar atmosphere (e.g., Patent Literature 1) has been suggested. Further, a method for growing a silicon single crystal having no grown-in defect such as a COP or a OSF nucleus present therein (which will be referred to as a perfect crystal hereinafter) by controlling growth conditions of the CZ method has been also suggested (e.g., Patent Literature 2).
Besides, there is a method for performing epitaxial growth on a silicon single crystal wafer and using an epitaxial layer as a DZ layer.
The control over BMDs is important to all devices, and it is particularly important to a solid-state image pickup device. That is because the solid-state image pickup device which is a photoelectric conversion element generates electric charges in accordance with intensity of light that has hit upon an imaging surface and converts the light into an electrical signal. Therefore, it is desirable for an electric charge amount on an imaging plane when light is shielded, i.e., when light does not strike at all to be “zero”. The electric charge amount is measured as a current, and it is desirable for the current when the light is shielded, i.e., a dark current to be as small as possible. However, when metal contamination or a grown-in defect is present in a photodiode region formed in a wafer surface layer, a deep level is formed in a forbidden band of a semiconductor. As a result, electric charges are generated through a defect even though light is not applied. This is known as a generation/recombination current, and this current degrades dark current characteristics, i.e., reduces electrical characteristics of the solid-state image sensing device.
However, even though metal contamination is introduced in a solid-state image pickup device fabrication process, if a BMD is formed at a position deeper than a device forming region, the BMD removes (getters) a metal contamination element from the wafer surface layer portion, and hence degradation of the electrical characteristics can be avoided.
To getter, a higher total volume of the BMDs (which is comparable to density×a BMD size per one BMD) is desirable, and having the BMD formed at a position that is close to the device forming region as much as possible (proximity gettering) is desirable. That is because, to getter a contamination element such as a metal, the contamination element must diffuse to a position of the BMD as a getter site during a heat treatment, but a diffusion distance of the contamination element tends to be shortened with lowering of a temperature/a time of a recent device process.
On the other hand, when the BMD size is too large, the BMD itself serves as a dislocation generation source, an adverse effect, i.e., deforming a wafer during a heat treatment in device manufacturing process and a reduction in yield rate arises by lowering of a device pattern matching accuracy in a photolithography process, and hence the size must be suppressed to a predetermined size or less. As described above, it is necessary that the density and the size of the BMD are controlled in a given fixed range. This can be likewise applied to a memory device.
An intrinsic gettering method (which will be referred to as an “IG method” hereinafter) for performing an oxygen precipitation heat treatment before epitaxial growth or the like and forming a BMD in a bulk can be applied to a silicon single crystal wafer that is used for the solid-state image pickup device. However, since the IG method requires a high-temperature/long-time heat treatment, there is concern in terms of cost or concern that the metal contamination is apt to occur during the heat treatment or slip might occur due to the heat treatment. Therefore, in recent years, a wafer obtained by forming an epitaxial layer formed on the wafer sliced out from a crystal in which carbon (C) is doped at the time of growing a silicon single crystal by the CZ method is often adopted. Although a BMD is not formed in this wafer at a shipping stage as a wafer, carbon is present in the wafer, and hence the wafer has characteristics that oxygen precipitation is apt to occur at a relatively low temperature, i.e., 400 to 800° C. and the BMD is easily formed by a heat treatment in the solid-state image pickup device fabrication process.
On the other hand, in case of a memory device, a silicon single crystal wafer that is sliced out from a perfect crystal and fabricated is widely adopted. Furthermore, a structure obtained by forming a very shallow grove that is called an STI (Shallow Trench Isolation) as element isolation and filling the inside of the groove with an oxide film is adopted. However, there is a problem that since a volume of the oxide film changes during a process of annealing the oxide film buried inside, large stress is generated around the STI, and a dislocation is thereby apt to occur from a corner portion of the STI. To alleviate this stress or pin the dislocation, a BMD having high density and a precipitous profile at a position close to an STI bottom portion is effective (Patent Literature 3).
Patent Literature 1: Japanese Unexamined Patent Application Publication No. 2002-353225
Patent Literature 2: Japanese Unexamined Patent Application Publication No. Hei 08-330316
Patent Literature 3: US 2001/0055689
Patent Literature 4: Japanese Unexamined Patent Application Publication No. Hei 11-116390
Patent Literature 5: Japanese Patent No. 3763629
Patent Literature 6: Japanese Unexamined Patent Application Publication No. 2010-40587
Patent Literature 7: Japanese Unexamined Patent Application Publication No. 2009-170656
Patent Literature 8: Japanese Unexamined Patent Application Publication No. 2001-203210
Patent Literature 9: Japanese Unexamined Patent Application Publication No. 2003-297839
Patent Literature 10: WO 2010/119614